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參數(shù)資料
| 型號： | K4S560432D-TC1H |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 16米x 4位× 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 121K |
| 代理商： | K4S560432D-TC1H |
K4S560432D
CMOS SDRAM
Rev. 0.0 Jan. 2002
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
Version
Unit
Note
-7C
-75
-1H
-1L
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
100
90
90
90
mA
1
Precharge standby cur-
rent in power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
2
mA
I
CC2
PS
2
Precharge standby cur-
rent in non power-down
mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
20
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
10
Active standby current in
power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
6
mA
I
CC3
PS
6
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
30
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
25
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4banks Activated.
t
CCD
= 2CLKs
110
110
100
100
mA
1
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
220
200
190
190
mA
2
Self refresh current
I
CC6
CKE
≤
0.2V
C
3
mA
3
L
1
mA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S560432D-TC**
4. K4S560432D-TL**
5. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
Notes :
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PDF描述 |
|---|---|
| K4S560432D-TC1L | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TC75 | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TC7C | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TL1H | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TL1L | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S560432D-TC1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TC75 | 制造商:Samsung Semiconductor 功能描述:DRAM Chip SDRAM 256M-Bit 64Mx4 3.3V 54-Pin TSOP-II |
| K4S560432D-TC7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TL1H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TL1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
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