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參數(shù)資料
| 型號(hào)： | K4S560432D-TL1L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 16米x 4位× 4銀行同步DRAM LVTTL |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 121K |
| 代理商： | K4S560432D-TL1L |
K4S560432D
CMOS SDRAM
Rev. 0.0 Jan. 2002
The K4S560432D is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 16,785,216 words by 4bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
16M x 4Bit x 4 Banks Synchronous DRAM
Part No.
Max Freq.
133MHz(CL=2)
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Interface
Package
K4S560432D-TC/L7C
K4S560432D-TC/L75
K4S560432D-TC/L1H
K4S560432D-TC/L1L
LVTTL
54pin
TSOP(II)
Bank Select
Data Input Register
16M x 4
16M x 4
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
16M x 4
16M x 4
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
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| K4S560432D-TL75 | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TL7C | 16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S561632E-TL75 | 256Mb E-die SDRAM Specification |
| K4S561632E-TC60 | 256Mb E-die SDRAM Specification |
| K4S561632E-TC75 | 256Mb E-die SDRAM Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S560432D-TL75 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432D-TL7C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16M x 4bit x 4 Banks Synchronous DRAM LVTTL |
| K4S560432E-NC | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:256Mb E-die SDRAM Specification 54pin sTSOP-II |
| K4S560432E-NC75 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:256Mb E-die SDRAM Specification 54pin sTSOP-II |
| K4S560432E-NL75 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:256Mb E-die SDRAM Specification 54pin sTSOP-II |
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