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參數(shù)資料
| 型號： | K4S643232E-TC50 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | K4S643232E-TC50 |
K4S643232E
CMOS SDRAM
- 9 -
Rev. 1.3 (Oct. 2001)
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
Parameter
Symbol
Version
-55
11
16.5
16.5
38.5
100
55
Unit
-45
9
18
18
40.5
-50
10
15
15
40
-60
12
18
18
42
-70
14
20
20
49
Row active to row active delay t
RRD(min)
RAS to CAS delay
Row precharge time
ns
ns
ns
ns
us
ns
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC
(
min
)
Row active time
Row cycle time
58.5
55
60
70
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-45
-50
-55
-60
-70
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
4.5
1000
5
1000
5.5
1000
6
1000
7
1000
ns
1
CAS Latency=2
10
10
10
10
10
CLK to valid
output delay
CAS Latency=3
t
SAC
-
4.0
-
4.5
-
5.0
-
5.5
-
5.5
ns
1, 2
CAS Latency=2
-
6
-
6
-
6
-
6
-
6
Output data hold time
t
OH
2
-
2
-
2
-
2
-
2
-
ns
2
CLK high pulse
width
CAS Latency=3
t
CH
1.75
-
2
-
2
-
2.5
-
3
-
ns
3
CAS Latency=2
3
-
3
-
3
-
3
-
3
-
CLK low
pulse width
CAS Latency=3
t
CL
1.75
-
2
-
2
-
2.5
-
3
-
ns
3
CAS Latency=2
3
-
3
-
3
-
3
-
3
-
Input setup time
CAS Latency=3
t
SS
1.2
-
1.5
-
1.5
-
1.5
-
1.75
-
ns
3
CAS Latency=2
2.5
-
2.5
-
2.5
-
2.5
-
2.5
-
Input hold time
t
SH
1
-
1
-
1
-
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
1
-
1
-
1
-
1
-
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
-
4.0
-
4.5
-
5.0
-
5.5
-
5.5
ns
-
CAS latency=2
-
6
-
6
-
6
-
6
-
6
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| K4S643232E-TC55 | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| K4S643232E-TC60 | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S643232E-TC55 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| K4S643232E-TC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| K4S643232ETC70 | 制造商:Samsung Semiconductor 功能描述: |
| K4S643232E-TC70 | 制造商:Samsung Electro-Mechanics 功能描述:SDRAM, 2M x 32, 86 Pin, Plastic, TSSOP |
| K4S643232E-TC70000 | 制造商:Samsung Semiconductor 功能描述: |
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