參數(shù)資料
型號(hào): K6X8008T2B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CMOS SRAM
中文描述: CMOS SRAM的
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 129K
代理商: K6X8008T2B
K6X8008T2B Family
Revision 1.0
September 2003
5
CMOS SRAM
C
L
1
)
1.Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
Vcc-0.2V,CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
Vcc-0.2V(CS
2
controlled).
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
1.5
-
3.6
V
Data retention current
I
DR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
K6X8008T2B-F
-
-
6
μ
A
K6X8008T2B-Q
10
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
AC CHARACTERISTICS
(V
CC
=2.7~3.6V, Industrial product: T
A
=-40 to 85
°
C, Automotive product: T
A
=-40 to 125
°
C)
1. Voltage range is 3.0V~3.6V for industrial product.
Parameter List
Symbol
Speed Bins
Units
55ns
1
)
70ns
Min
Max
Min
Max
Read
Read Cycle Time
t
RC
55
-
70
-
ns
Address Access Time
t
AA
-
55
-
70
ns
Chip Select to Output
t
CO
-
55
-
70
ns
Output Enable to Valid Output
t
OE
-
25
-
35
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
20
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
20
0
25
ns
Output Hold from Address Change
t
OH
10
-
10
-
ns
Write
Write Cycle Time
t
WC
55
-
70
-
ns
Chip Select to End of Write
t
CW
45
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
45
-
60
-
ns
Write Pulse Width
t
WP
40
-
50
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
20
0
20
ns
Data to Write Time Overlap
t
DW
25
-
30
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns
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