參數(shù)資料
型號(hào): K7D323674A-HC37
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 32Mb A-die DDR SRAM Specification
中文描述: 32兆甲芯片的DDR SRAM的規(guī)范
文件頁(yè)數(shù): 5/19頁(yè)
文件大小: 494K
代理商: K7D323674A-HC37
Rev 1.4
Oct. 2005
1Mx36 & 2Mx18 SRAM
- 5 -
K7D321874A
K7D323674A
FUNCTIONAL BLOCK DIAGRAM
K,K
B
1
B
3
B
2
Register
CE
Memory Array
1Mx36
or
(2Mx18)
Data Out
Data In
Advance
Control
SD/DD
Clock
Buffer
Synchronous
Select
&
R/W control
Internal
Clock
Generator
CE
R/W
LD
Data Output Strobe
Data Output Enable
State Machine
Strobe_out
S/A Array
2 : 1 MUX
Data In
Register
(2 stage)
Write Buffer
W/D
Array
Echo Clock
Output
36(or 18)x2
36(or 18)x2
36(or18)x2
36(or18)x2
XDIN
CQ,CQ
DQ
36(or 18)
Output
Buffer
Write
Address
CE
Burst
Counter
Register
(2 stage)
Address
Comparator
2:1
MUX
Dec.
20(or 21)
18(or 19)
18(or 19)
20(or 21)
(Burst Write
Address)
SA[0:20]( or SA[0:21])
(Burst Address)
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
Pin Description
K, K
Differential Clocks
TCK
JTAG Test Clock
SA
Synchronous Address Input
TMS
JTAG Test Mode Select
SA
0
, SA
1
Synchronous Burst Address Input (SA
0
= LSB)
TDI
JTAG Test Data Input
DQ
Synchronous Data I/O
TDO
JTAG Test Data Output
CQ, CQ
Differential Output Echo Clocks
V
REF
HSTL Input Reference Voltage
B
1
Load External Address
V
DD
Power Supply
B
2
Burst R/W Enable
V
DDQ
Output Power Supply
B
3
Single/Double Data Selection
V
SS
GND
LBO
Linear Burst Order
NC
No Connection
ZQ
Output Driver Impedance Control Input
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K7D323674A-HC40 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification
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