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參數(shù)資料
| 型號(hào)： | K7D323674A-HGC37 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Mb A-die DDR SRAM Specification |
| 中文描述： | 32兆甲芯片的DDR SRAM的規(guī)范 |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大?。?/td> | 494K |
| 代理商： | K7D323674A-HGC37 |
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Rev 1.4
Oct. 2005
1Mx36 & 2Mx18 SRAM
- 13
K7D321874A
K7D323674A
AC TIMING CHARACTERISTICS
Notes
:
1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table.
3. This parameter refers to CQ and CQ rising and falling edges.
4. This parameter is only for 32Mb density
5. K and K Clocks must be used differencitally to meet AC timing specifications.
PARAMETER
SYMBOL
-40
-37
-33
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time
t
KHKH
2.50
5.00
2.67
6.00
3.00
6.00
ns
1
Clock High Pulse Width
t
KHKL
1.15
1.25
1.40
ns
Clock Low Pulse Width
t
KLKH
1.15
1.25
1.40
ns
Setup Times
Address Setup Time
t
AVKH
0.30
0.33
0.35
ns
Control(B1,B2,B3) Setup Time
t
BVKH
0.30
0.33
0.35
ns
Data Setup Time
t
DVKX
0.20
0.25
0.30
ns
2
Hold Times
Address Hold Time
t
KHAX
0.30
0.33
0.35
ns
Control(B1,B2,B3) Hold Time
t
KHBX
0.30
0.33
0.35
ns
Data Hold Time
t
KXDX
0.20
0.25
0.30
ns
2
Output Times
Echo Clock High Pulse Width
t
CHCL
t
KHKL
-0.1
t
KHKL
+0.1
t
KHKL
-0.1
t
KHKL
+0.1
t
KHKL
-0.1
t
KHKL
+0.1
ns
2
Echo Clock Low Pulse Width
t
CLCH
t
KLKH
-0.1
t
KLKH
+0.1
t
KLKH
-0.1
t
KLKH
+0.1
t
KLKH
-0.1
t
KLKH
+0.1
ns
2
Clock Crossing to Echo Clock
t
CXCH
1.0
2.5
1.0
2.5
1.0
2.5
ns
3
Clock Crossing to Echo Clock
t
CXCL
1.0
2.5
1.0
2.5
1.0
2.5
ns
3
Echo Clock High to Output Vaild
t
CHQV
0.20
0.20
0.20
ns
Echo Clock Low to Output Valid
t
CLQV
0.20
0.20
0.20
ns
Echo Clock High to Output Hold
t
CHQX
-0.20
-0.20
-0.20
ns
Echo Clock Low to Output Hold
t
CLQX
-0.20
-0.20
-0.20
ns
Echo Clock High to Output High-Z
t
CHQZ
0.20
0.20
0.20
ns
Echo Clock High to Output Low-Z
t
CHLZ
-0.20
-0.20
-0.20
ns
50
50
AC TEST OUTPUT LOAD
25
5pF
DQ
0.75V
5pF
0.75V
50
50
0.75V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7D323674A-HGC40 | 32Mb A-die DDR SRAM Specification |
| K7D801871B-HC25 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC30 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 256Kx36 & 512Kx18 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7D323674A-HGC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
| K7D323674C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 SRAM |
| K7D801871B-HC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
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