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參數(shù)資料
| 型號(hào)： | K7D323674A-HGC37 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Mb A-die DDR SRAM Specification |
| 中文描述： | 32兆甲芯片的DDR SRAM的規(guī)范 |
| 文件頁(yè)數(shù)： | 16/19頁(yè) |
| 文件大?。?/td> | 494K |
| 代理商： | K7D323674A-HGC37 |
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Rev 1.4
Oct. 2005
1Mx36 & 2Mx18 SRAM
- 16
K7D321874A
K7D323674A
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to V
SS
to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to V
DD
through a resistor. TDO should be left
unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
SA
SA
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
0
1
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE
:
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. Input terminators are switched off.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to V
SS
when BYPASS instruction is
invoked.
The Bypass Register also holds serially loaded TDI when exiting the
Shift DR states.
4. SAMPLE instruction dose not places DQs in Hi-Z.
5. PRIVATE1 and PRIVATE2 are reserved for the exclusive use of SAM-
SUNG. This instruction should not be used.
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
EXTEST
Boundary Scan Register
1
0
0
1
IDCODE
Identification Register
2
0
1
0
SAMPLE-Z
Boundary Scan Register
1
0
1
1
PRIVATE3
Bypass Register
3,5
1
0
0
SAMPLE
Boundary Scan Register
4
1
0
1
PRIVATE2
Bypass Register
3,5
1
1
0
PRIVATE1
Bypass Register
3,5
1
1
1
BYPASS
Bypass Register
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7D323674A-HGC40 | 32Mb A-die DDR SRAM Specification |
| K7D801871B-HC25 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC30 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 256Kx36 & 512Kx18 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7D323674A-HGC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
| K7D323674C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 SRAM |
| K7D801871B-HC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
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