參數(shù)資料
型號: K7D323674A-HGC37
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 32Mb A-die DDR SRAM Specification
中文描述: 32兆甲芯片的DDR SRAM的規(guī)范
文件頁數(shù): 9/19頁
文件大?。?/td> 494K
代理商: K7D323674A-HGC37
Rev 1.4
Oct. 2005
1Mx36 & 2Mx18 SRAM
- 9 -
K7D321874A
K7D323674A
TRUTH TABLE
NOTE
: - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
K
B1
B2
B3
DQ
Operation
H
L
X
Hi-Z
No Operation, Pipeline High-Z
L
H
H
DOUT
Load Address, Single Read
L
H
L
DOUT
Load Address, Double Read
L
L
H
DIN
Load Address, Single Write
L
L
L
DIN
Load Address, Double Write
H
H
X
B
Increment Address, Continue
4 Burst Operation for Interleaved Burst (LBO = V
DDQ
)
NOTE
: - For Interleave Burst LBO = V
DDQ
is recommended. If LBO = V
DD
, it must not exceed 2.63V.
Interleaved Burst
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BURST SEQUENCE TABLE
4 Burst Operation for Linear Burst (LBO = V
SS
)
Linear Burst Mode
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
OUTPUT TRISTATE TRUTH TABLE
K
Operation
DQ (n)
DQ (n+1)
Write (B2=L)
X
High-Z
Deslect (NOP) (B1=H, B2=L)
X
High-Z
相關PDF資料
PDF描述
K7D323674A-HGC40 32Mb A-die DDR SRAM Specification
K7D801871B-HC25 256Kx36 & 512Kx18 SRAM
K7D801871B-HC30 256Kx36 & 512Kx18 SRAM
K7D801871B-HC33 256Kx36 & 512Kx18 SRAM
K7D801871B-HC35 256Kx36 & 512Kx18 SRAM
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K7D323674C 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 SRAM
K7D801871B-HC25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM
K7D801871B-HC30 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM
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