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參數(shù)資料
| 型號： | K7D323674A-HGC40 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Mb A-die DDR SRAM Specification |
| 中文描述： | 32兆甲芯片的DDR SRAM的規(guī)范 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 494K |
| 代理商： | K7D323674A-HGC40 |
Rev 1.4
Oct. 2005
1Mx36 & 2Mx18 SRAM
- 8 -
K7D321874A
K7D323674A
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least two NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and V
SS
, and
are equal to RQ/5. For example, 250
resistor will give an output impedance of 50
. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Output driver imped-
ance is updated every 64 clock cycles of Non-Read operation (Write or NOP) but since the echo clock drivers are in operation even
during Non-Read operation, the impedance is update only the drivers are not in operation. Therefore impedance updates for "0s" or
pull down drivers occur whenever the echo clock driver is driving "1s" or vice versa. Furthermore, to guarantee optimum output
driver impedance after power up, the SRAM need 2048 deselect (or write) cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
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PDF描述 |
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| K7D801871B-HC30 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC37 | 256Kx36 & 512Kx18 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7D323674C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 SRAM |
| K7D801871B-HC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
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