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參數(shù)資料
| 型號： | K7D323674A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Mb A-die DDR SRAM Specification |
| 中文描述： | 32兆甲芯片的DDR SRAM的規(guī)范 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 494K |
| 代理商： | K7D323674A |
Rev 1.4
Oct. 2005
1Mx36 & 2Mx18 SRAM
- 14
K7D321874A
K7D323674A
NOP
CONTINUE
K
K
B1
SA
t
AVKH
t
KHAX
CQ
NOP
1
2
3
4
5
6
7
8
10
12
11
B2
B3
CQ
DQ
READ
(burst of 4)
(burst of 4)
READ
(burst of 2)
READ
NOP
WRITE
CONTINUE
WRITE
(burst of 4)
READ
9
CONTINUE
READ
READ
(burst of 4)
CONTINUE
READ
A
0
A
1
A
2
A
3
Q
X2
Q
01
Q
02
Q
03
Q
04
Q
51
Q
52
Q
53
Q
54
Q
11
Q
12
D
21
D
23
D
24
D
22
Q
31
t
BVKH
t
KHBX
t
CHQZ
t
KXCH
t
CHLZ
t
CHQV
t
CHQX
t
DVKH
t
KHDX
t
KHKH
UNDEFINED
DON’T CARE
A
5
NOTE
1. Q
01
refers to output from address A. Q
02
refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
t
CLQV
t
CLQX
t
KXCL
t
CHCL
t
CLCH
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|---|---|
| K7D323674A-HC33 | 32Mb A-die DDR SRAM Specification |
| K7D323674A-HC37 | 32Mb A-die DDR SRAM Specification |
| K7D323674A-HC40 | 32Mb A-die DDR SRAM Specification |
| K7D323674A-HGC33 | 32Mb A-die DDR SRAM Specification |
| K7D323674A-HGC37 | 32Mb A-die DDR SRAM Specification |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K7D323674A-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
| K7D323674A-HC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
| K7D323674A-HC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
| K7D323674A-HGC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
| K7D323674A-HGC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Mb A-die DDR SRAM Specification |
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