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參數(shù)資料
| 型號： | K7D801871B-HC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 270K |
| 代理商： | K7D801871B-HC25 |
Rev 4.0
256Kx36 & 512Kx18 SRAM
- 12
January. 2002
K7D801871B
K7D803671B
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
NOTE
:
1. Q
01
refers to output from address A
0
. Q
02
refers to output from the next internal burst address following A
0
, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
Continue assertions constitute invalid operations.
4. This device will have an address wraparound if further Continues are applied.
NOP
CONTINUE
t
KHKH
t
AVKH
t
KHAX
NOP
1
2
3
4
5
6
7
8
10
12
11
READ
(burst of 4)
(burst of 2)
READ
READ
(burst of 1)
NOP
WRITE
CONTINUE
WRITE
(burst of 2)
READ
9
CONTINUE
READ
CONTINUE
READ
CONTINUE
READ
Q
X1
D
22
D
21
t
BVKH
t
KHBX
t
CHQZ
t
KXCH
t
CHLZ
t
CHQV
t
CHQX
t
GHQZ
t
GHQX
t
DVKH
t
KHDX
t
GLQX
t
GLQV
t
KLKH
Q
31
Q
01
Q
02
Q
03
Q
04
Q
11
t
KHKL
K
K
B1
G
SA
B2
B3
DQ
CQ
CQ
A
0
A
1
A
2
A
3
UNDEFINED
DON’T CARE
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| K7D801871B-HC35 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC37 | 256Kx36 & 512Kx18 SRAM |
| K7D803671B | 256Kx36 & 512Kx18 SRAM |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7D801871B-HC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D803671B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
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