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參數(shù)資料
| 型號(hào)： | K7I321882M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | DRAM |
| 英文描述： | 1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | K7I321882M |
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1Mx36 & 2Mx18 DDRII CIO b2 SRAM
- 7 -
Rev 2.1
July. 2004
K7I323682M
K7I321882M
STATE DIAGRAM
Notes
: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High.
3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low
LOAD
LOAD
LOAD
LOAD
POWER-UP
NOP
LOAD NEW ADDRESS
DDR READ
DDR WRITE
LOAD
LOAD
READ
WRITE
LINEAR BURST SEQUENCE TABLE
BURST SEQUENCE
Case 1
SA
0
0
1
Case 2
SA
0
1
0
First Address
Second Address
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PDF描述 |
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| K7I323682M | 1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
| K7J161882B | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| K7J163682B | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| K7J321882M | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J323682M | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7I321884C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 DDRII CIO b4 SRAM |
| K7I323682C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
| K7I323682C-FC20000 | 制造商:Samsung Semiconductor 功能描述:32MSYNC DDRII, COMMON I/O SRAM 1MX36FBGA - Bulk |
| K7I323682C-FC20T00 | 制造商:Samsung Semiconductor 功能描述:32MSYNC DDRII, COMMON I/O SRAM 1MX36FBGA, T/R - Tape and Reel |
| K7I323682C-FC30000 | 制造商:Samsung 功能描述:32M 32MSYNC DOUBLE DATA RATE II, COMMON I/O X36 FBGA - Trays |
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