- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374293 > K7J163682B (SAMSUNG SEMICONDUCTOR CO. LTD.) 512Kx36 & 1Mx18 DDR II SIO b2 SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | K7J163682B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 374K |
| 代理商： | K7J163682B |
512Kx36 & 1Mx18 DDR II SIO b2 SRAM
- 2 -
Rev 3.1
July. 2004
K7J163682B
K7J161882B
512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM
FEATURES
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O
.
Separate independent read and write data ports
HSTL I/O
Synchronous pipeline read with self timed late write.
Registered address, control and data input/output.
Full data coherency, providing most current data.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write (x18, x36) function.
Simple depth expansion with no data contention.
Programmable output impedance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball array FBGA) with body size of 13x15mm
FUNCTIONAL BLOCK DIAGRAM
R/W
LD
BW
X
ADDRESS
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
512kx36
(1Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
36 (or 18)
4(or 2)
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device
18
18 (or 19)
Q(Data Out)
36 (or 18)
36
72
(or 36)
(Echo Clock out)
CQ, CQ
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7J163682B-FC30
3.3
0.45
ns
K7J163682B-FC25
4.0
0.45
ns
K7J163682B-FC20
5.0
0.45
ns
K7J163682B-FC16
6.0
0.50
ns
X18
K7J161882B-FC30
3.3
0.45
ns
K7J161882B-FC25
4.0
0.45
ns
K7J161882B-FC20
5.0
0.45
ns
K7J161882B-FC16
6.0
0.50
ns
DDR II SRAM and Double Data Rate II comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 18)
(or 18)
36
(or 19)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7J321882M | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J323682M | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J641882M | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC16 | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC20 | 72Mb M-die DDRII SRAM Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7J163682B-FC25000 | 制造商:Samsung Semiconductor 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA |
| K7J321882C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J321882C-FC27000 | 制造商:Samsung Semiconductor 功能描述:32M 32MSYNC DOUBLE DATA RATE, SEPARATE I/O X18 FBGA - Trays |
| K7J321882C-FC30T00 | 制造商:Samsung Semiconductor 功能描述:32MSYNC DDRII, SEPARATE I/O SRAMX18FBGA, T/R - Tape and Reel |
| K7J321882M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。