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參數(shù)資料
| 型號(hào)： | K7J323682M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 305K |
| 代理商： | K7J323682M |
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 5 -
Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
The K7J323682M and K7J321882M are 37,748,736-bits DDR Separate I/O
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7J323682M and 2,097,152 words by 18 bits for K7J321882M.
The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports.
Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports
eliminate bus turn around cycle.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW
0
and BW
1
( BW
2
and BW
3)
pins for x18 ( x36 ) device.
Nybble write operation is supported with NW
0
and NW
1
pins for x8 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7J323682M and K7J321882M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the LD is disabled after a read operation, the K7J323682M and K7J321882M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
Power-Up/Power-Down Supply Voltage Sequencing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7J641882M | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC16 | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC20 | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC25 | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC30 | 72Mb M-die DDRII SRAM Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7-J5 | 制造商:MITSUMI 制造商全稱:Mitsumi Electronics, Corp. 功能描述:Adjustable Type Coils |
| K7J641882M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
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