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參數(shù)資料
| 型號： | K7J641882M-FC16 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 72Mb M-die DDRII SRAM Specification |
| 中文描述： | 72Mb的M -模條DDRII規(guī)格的SRAM |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 326K |
| 代理商： | K7J641882M-FC16 |
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
K7J643682M
K7J641882M
- 13 -
Rev 1.0
Aug. 2005
TIMING WAVE FORMS OF READ,WRITE AND NOP
D3-1
1
2
3
4
5
6
7
8
NOP
READ
(burst of 2)
READ
(burst of 2)
WRITE
(burst of 2)
WRITE
(burst of 2)
READ
(burst of 2)
NOP
NOP
D3-2
D4-1
D4-2
Q1-1
Q1-2
Q2-1
Q2-2
t
DVKH
t
KHDX
t
DVKH
t
KHDX
t
CHQV
t
CHQV
t
CHQX1
t
CHQX
t
CHQX
t
CHQZ
Q5-1
Q5-2
t
CQHQV
t
KHKL
t
KLKH
t
KHKH
t
KHKH
t
CHCQV
t
CHCQX
t
CHCQX
t
KHCH
t
KHCH
t
KHKL
t
KLKH
t
KHKH
t
KHKH
t
IVKH
t
KHIX
A2
A1
A3
A4
A5
K
LD
R/W
K
A
D
Q
C
C
CQ
CQ
t
AVKH
t
KHAX
t
CHCQV
Qxx
Note
:
1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
3. D3-1 refers to input to address A3+0, D3-2 refers to input to address A3+1, i.e the next internal burst address following A3+0.
4. If address A4=A5, data Q5-1=D4-1, data Q5-2=D4-2.
Write data is forwarded immediately as read results.
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| K7J641882M-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
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| K7J641882M-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J641882M-FECI16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J641882M-FECI20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
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