參數(shù)資料
型號(hào)： K7J641882M-FECI16
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 72Mb M-die DDRII SRAM Specification
中文描述： 72Mb的M -模條DDRII規(guī)格的SRAM
文件頁(yè)數(shù)： 7/17頁(yè)
文件大?。?/td> 326K
代理商： K7J641882M-FECI16
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
K7J643682M
K7J641882M
- 7 -
Rev 1.0
Aug. 2005
Single Clock Mode
K7J643682M and K7J641882M can be operated with the single clock pair K and K, insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up
and must be maintained high during operation.
After power up, this device can
′
t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Clock Consideration
K7J643682M and K7J641882M utlizes internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
Power-Up/Power-Down Supply Voltage Sequencing
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
SS
through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
resistor will give an output impedance of 50
.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous
behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
相關(guān)PDF資料
PDF描述
K7J641882M-FECI20 72Mb M-die DDRII SRAM Specification
K7J641882M-FECI25 72Mb M-die DDRII SRAM Specification
K7J641882M-FECI30 72Mb M-die DDRII SRAM Specification
K7J643682M 72Mb M-die DDRII SRAM Specification
K7J643682M-FC16 72Mb M-die DDRII SRAM Specification
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K7J641882M-FECI20 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification
K7J641882M-FECI25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification
K7J641882M-FECI30 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification
K7J643682M 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification
K7J643682M_07 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx36 & 4Mx18 DDR II SIO b2 SRAM
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