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參數(shù)資料
| 型號(hào)： | K7J643682M-FECI20 |
| 廠(chǎng)商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 72Mb M-die DDRII SRAM Specification |
| 中文描述： | 72Mb的M -模條DDRII規(guī)格的SRAM |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 326K |
| 代理商： | K7J643682M-FECI20 |
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2Mx36 & 4Mx18 DDR II SIO b2 SRAM
K7J643682M
K7J641882M
- 3 -
Rev 1.0
Aug. 2005
2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM
FEATURES
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O
.
Separate independent read and write data ports
HSTL I/O
Synchronous pipeline read with self timed late write.
Registered address, control and data input/output.
Full data coherency, providing most current data.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write function.
Simple depth expansion with no data contention.
Programmable output impedance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
& Lead Free
FUNCTIONAL BLOCK DIAGRAM
R/W
LD
BW
X
ADDRESS
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
2Mx36
(4Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
36 (or 18)
4(or 2)
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device.
20
20 (or 21)
Q(Data Out)
36 (or 18)
36
72
(or 36)
(Echo Clock out)
CQ, CQ
* E : Lead Free Package
* I : Industrial Temperature
Org.
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7J643682M-F(E)C(I)30
3.3
0.45
ns
K7J643682M-F(E)C(I)25
4.0
0.45
ns
K7J643682M-F(E)C(I)20
5.0
0.45
ns
K7J643682M-F(E)C(I)16
6.0
0.50
ns
X18
K7J641882M-F(E)C(I)30
3.3
0.45
ns
K7J641882M-F(E)C(I)25
4.0
0.45
ns
K7J641882M-F(E)C(I)20
5.0
0.45
ns
K7J641882M-F(E)C(I)16
6.0
0.50
ns
DDR II SRAM and Double Data Rate II comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 18)
(or 18)
36
(or 21)
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| K7J643682M-FECI25 | 72Mb M-die DDRII SRAM Specification |
| K7J643682M-FECI30 | 72Mb M-die DDRII SRAM Specification |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7J643682M-FECI25 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J643682M-FECI30 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7K1618T2C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM |
| K7K1618U2C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM |
| K7K1636T2C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM |
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