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參數(shù)資料
| 型號： | K7J643682M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 72Mb M-die DDRII SRAM Specification |
| 中文描述： | 72Mb的M -模條DDRII規(guī)格的SRAM |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 326K |
| 代理商： | K7J643682M |
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
K7J643682M
K7J641882M
- 5 -
Rev 1.0
Aug. 2005
PIN CONFIGURATIONS
(TOP VIEW)
K7J641882M(4Mx18)
Notes:
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
2. BW
0
controls write to D0:D8 and BW
1
controls write to D9:D17.
1
2
3
4
5
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
8
9
10
SA
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
V
SS/
SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
SA
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
PIN NAME
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value
and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
NOTE
1
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
D0-17
Data Inputs
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
Data Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW
0
, BW
1
V
REF
ZQ
V
DD
7B, 5A
2H,10H
11H
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
V
DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V
SS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
TDI
TCK
TDO
10R
11R
2R
1R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
NC
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
No Connect
3
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| K7J643682M_07 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx36 & 4Mx18 DDR II SIO b2 SRAM |
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| K7J643682M-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
| K7J643682M-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb M-die DDRII SRAM Specification |
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