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參數(shù)資料
| 型號： | K7M803625A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Evaluation Module for TPS650732 5-Channel Power Management IC |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 321K |
| 代理商： | K7M803625A |
256Kx36 & 512Kx18 Flow-Through N
t
RAM
TM
- 2 -
Rev 1.0
July 2000
K7M801825A
K7M803625A
256Kx36 & 512Kx18-Bit Flow Through N
t
RAM
TM
The K7M803625A and K7M801825A are 9,437,184-bit Syn-
chronous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M803625A and K7M801825A are implemented with
SAMSUNG
′
s high performance CMOS technology and is avail-
able in 100pin TQFP and 119BGA packages. Multiple power
and ground pins minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
Byte Writable Function.
Ε
nable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention .
A interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package) .
LOGIC BLOCK DIAGRAM
FAST ACCESS TIMES
Parameter
Symbol -75 -85 -90 -10 Unit
Cycle Time
t
CYC
8.5
10
10
12
ns
Clock Access Time
t
CD
7.5 8.5 9.0 10.0 ns
Output Enable Access Time
t
OE
3.5 3.5 3.5 3.5
ns
N
t
RAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
0
~ DQd
7
or
DQa
0
~ DQb
8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
BUFFER
DATA-IN
REGISTER
K
BURST
ADDRESS
COUNTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:17]or
A [0:18]
LBO
A
0
~A
1
A
2
~A
17
or
A
2
~A
18
256Kx36 , 512Kx18
MEMORY
ARRAY
相關PDF資料 |
PDF描述 |
|---|---|
| K7M801825B | 256Kx36 & 512Kx18-Bit Flow Through NtRAM |
| K7M803625B | 256Kx36 & 512Kx18-Bit Flow Through NtRAM |
| K7N161801M | 512Kx36 & 1Mx18-Bit Pipelined NtRAM TM |
| K7N163601M | 512Kx36 & 1Mx18-Bit Pipelined NtRAM TM |
| K7N161845M | 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K7M803625B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Flow Through NtRAM |
| K7M803625B_06 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 Flow-Through NtRAM |
| K7M803625B-QC65 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAMTM |
| K7M803625B-QC65/75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Flow Through NtRAM |
| K7M803625B-QC75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAM |
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