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參數(shù)資料
| 型號： | K7N403601B-QC13 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36 & 256Kx18 Pipelined NtRAMTM |
| 中文描述： | 128K × 36至 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 387K |
| 代理商： | K7N403601B-QC13 |
K7N403609B
K7N401809B
128Kx36 & 256Kx18 Pipelined N
t
RAM
TM
- 3 -
Rev 2.0
Nov. 2003
128Kx36 & 256Kx18-Bit Pipelined N
t
RAM
TM
The K7N403609B and K7N401809B are 4,718,592 bits Syn-
chronous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory
utilizes all the bandwidth in any combination of operating
cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incomming sig-
nals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge trigered output register and then released
to the output bufferes at the next rising edge of clock.
The K7N403609B and K7N401809B are implemented with
SAMSUNG
′
s high performance CMOS technology and is
available in 100pin TQFP packages. Multiple power and
ground pins minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
V
DD
=3.3V+0.165V/-0.165V Power Supply.
V
DDQ
Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no datacon-
tention.
Α
interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A Package.
Operating in commeical and industrial temperature range.
LOGIC BLOCK DIAGRAM
FAST ACCESS TIMES
PARAMETER
Symbol
-20
Unit
Cycle Time
tCYC
5.0
ns
Clock Access Time
tCD
2.8
ns
Output Enable Access Time
tOE
2.8
ns
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
~ DQd
or
DQa
0
~ DQb
8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:16]or
A [0:17]
LBO
A
0
~A
1
A
2
~A
16
or
A
2
~A
17
128Kx36 , 256Kx18
MEMORY
ARRAY
N
t
RAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
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|---|---|
| K7N403601B-QC13T00 | 制造商:Samsung Semiconductor 功能描述: |
| K7N403601B-QI13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM |
| K7N403601M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM-TM |
| K7N403609B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAMTM |
| K7N403609B_06 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM |
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