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參數(shù)資料
| 型號(hào)： | K7N801845B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM |
| 中文描述： | 256Kx36 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 379K |
| 代理商： | K7N801845B |
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256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 3 -
Rev 3.0
Nov 2003
K7N801845B
K7N803645B
256Kx36 & 512Kx18-Bit Pipelined N
t
RAM
TM
The K7N803645B and K7N801845B are 9,437,184 bits Syn-
chronous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory
utilizes all the bandwidth in any combination of operating
cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803645B and K7N801845B are implemented with
SAMSUNG
′
s high performance CMOS technology and is
available in 100pin TQFP and Multiple power and ground pins
minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
2.5V
±
5% Power Supply.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention .
Α
interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A
Operating in commeical and industrial temperature range.
LOGIC BLOCK DIAGRAM
FAST ACCESS TIMES
PARAMETER
Symbol
-16
-13
Unit
Cycle Time
t
CYC
6.0
7.5
ns
Clock Access Time
t
CD
3.5
4.2
ns
Output Enable Access Time
t
OE
3.5
3.8
ns
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
0
~ DQd
7
or
DQa
0
~ DQb
8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:17]or
A [0:18]
LBO
A
0
~A
1
A
2
~A
17
or
A
2
~A
18
256Kx36 , 512Kx18
MEMORY
ARRAY
N
t
RAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7N803645M | 256K X 36 & 512K X 18 PIPELINED N-T RAM - TM |
| K7N801845M | 256K X 36 & 512K X 18 PIPELINED N-T RAM - TM |
| K7P403622B-HC20 | 128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| K7P403622B-HC25 | 128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| K7P403622B | 128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7N801845B-QC13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAM |
| K7N801845B-QC13000 | 制造商:Samsung Semiconductor 功能描述:SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 4.2ns 100-Pin TQFP Tray |
| K7N801845B-QC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAM |
| K7N801845B-QC16/13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Flow Through NtRAM |
| K7N801845M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256K X 36 & 512K X 18 PIPELINED N-T RAM - TM |
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