參數(shù)資料
型號(hào)： K7N801845M
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256K X 36 & 512K X 18 PIPELINED N-T RAM - TM
中文描述： 256 × 36
文件頁(yè)數(shù)： 1/18頁(yè)
文件大小： 282K
代理商： K7N801845M
K7N803645M
K7N801845M
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 1 -
Rev 3.0
November 1999
Document Title
256Kx36 & 512Kx18-Bit Pipelined N
t
RAM
TM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
History
1. Initial document.
1. Changed speed bin from 167MHz to 150MHz
2. Changed DC Parameters;
I
CC
: from 400mA to 450mA , ISB : from 60mA to 20mA
I
SB2
: from 50mA to 85mA
1. Changed speed bin from 150MHz to 167MHz
2. Changed Power from 3.3V to 2.5V
3. Changed N.C pins to Power and ZZ Pin #14, #16, #64, #66
4. Changed some control pin names.
from CEN to CKE, from BWEx to BWx
5. Modify absolute maximum ratings
V
DD
; from 4.0V to 3.6V, V
IN
; from 4.6V to 3.6V
6. Changed DC parameters
I
SB
; from 20mA to 80mA, I
SB2
; from 85mA to 10mA
V
OL
; from 0.4V to 0.2V, V
OH
; from 2.4V to 2.0V
V
IL
; from 0.8V to 0.7V, V
IH
; from 2.0V to 1.7V
7. A
DD
the sleep mode timing and characteristics
CKE controlled timing and CS controlled timing
1. Removed speed bin 167MHz
2.Changed AC parameters
t
HZOE
; from 4.0 to 3.5 , t
HZC
;from 4.0 to 3.5 at -75
t
HZOE
; from 5.0 to 3.5 , t
HZC
;from 5.0 to 3.5 , t
CL/H
; 4.0 to 3.0 at -10
3.Modify Sleep Mode Waveform.
Changed Sleep Mode Electrical Characteristics .
t
PDS
;from Max 2cycle to Min 2cycle
t
PUS
; from Max 2cycle to Min 2cycle
1.Modify from ADV to ADV at timing.
2.A
DD
the Trade Mark( N
t
RAM
TM
)
1. Changed DC parameters
I
SB1
; from 10mA to 20mA, I
SB2
; from 10mA to 20mA
1. Changed t
CD
,t
OE
from 4.0ns to 4.2ns at -75.
1. Changed DC condition at Icc and parameters
I
CC
; from 420mA to 320mA at -67 , from 370mA to 300mA at -75
from 300mA to 250mA at -10.
I
SB
; from 70mA to 60mA at -67 , from 60mA to 50mA at -75
from 50mA to 40mA at -10.
1.Changed V
OL
Max value from 0.2V to 0.4V .
1. Add 119BGA(7x17 Ball Grid Array Package) .
1. Final spec release
1. Add t
CYC
167Mhz.
Draft Date
September. 1997
November. 1997
March. 11. 1998
April. 11. 1998
June. 02. 1998
Aug. 19. 1998
Sep. 28. 1998
Nov. 10. 1998
Dec. 23. 1998
Mar. 03. 1999
April. 01. 1999
Oct. 30. 1999
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