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參數(shù)資料
| 型號： | K7N803645M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K X 36 & 512K X 18 PIPELINED N-T RAM - TM |
| 中文描述： | 256 × 36 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 282K |
| 代理商： | K7N803645M |
K7N803645M
K7N801845M
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 12 -
Rev 3.0
November 1999
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during t
PUS
, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
(V
DD
,V
DDQ
=2.5V
±
5%)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
Current during SLEEP MODE
ZZ
≥
V
IH
I
SB2
10
mA
ZZ active to input ignored
t
PDS
2
cycle
ZZ inactive to input sampled
ZZ active to SLEEP current
t
PUS
2
cycle
t
ZZI
2
cycle
ZZ inactive to exit SLEEP current
t
RZZI
0
K
t
PDS
ZZ setup cycle
t
RZZI
ZZ
Isupply
All inputs
(except ZZ)
Outputs
(Q)
t
ZZI
t
PUS
ZZ recovery cycle
Deselect or Read Only
High-Z
DON
′
T CARE
I
SB2
SLEEP MODE WAVEFORM
Normal
operation
cycle
Deselect or Read Only
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| K7N803649B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 Pipelined NtRAM |
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| K7P161866A-HC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 AND 1Mx18 Synchronous Pipelined SRAM |
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