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參數(shù)資料
| 型號(hào)： | K7P403622B-HC16 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| 中文描述： | 128K × 36至 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大小： | 280K |
| 代理商： | K7P403622B-HC16 |
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Rev 1.2
Jul. 2003
- 8 -
K7P401822B
128Kx36 & 256Kx18 SRAM
K7P403622B
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)
1
2
3
4
5
6
7
8
K
SAn
SS
SW
SWx
DQn
NOTE
1. D
3
is the input data written in memory location A
3
.
2. Q
4
is the output data read from the write data buffer(not from the cell array), as a result of address A
4
being a match from the
last write cycle address.
A
1
A
2
A
3
A
4
A
5
A
4
A
6
A
7
Q
1
D
3
D
4
Q
5
Q
4
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)
1
2
3
4
5
6
7
8
K
SAn
G
SW
SWx
DQn
NOTE
1. D
3
is the input data written in memory location A
3
.
2. Q
4
is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
A
1
A
2
A
3
A
4
A
5
A
4
A
6
A
7
Q
2
Q
1
D
3
D
4
Q
5
Q
4
Q
2
t
KHKH
t
AVKH
t
KHAX
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
WVKH
t
KHWX
t
KHQX1
t
KHQX
t
WVKH
t
KHWX
t
KHQV
t
KHDX
t
KHQZ
t
DVKH
t
KHDX
t
KHKH
t
GHQZ
t
GLQX
t
GLQV
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| K7Q161854A | 512Kx36-bit, 1Mx18-bit QDR SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7P403622B-HC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| K7P403622B-HC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| K7P403622M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| K7P403622M-H16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| K7P403622M-H19 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
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