參數(shù)資料
型號: K7Q161862B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Kx36 & 1Mx18 QDRTM b2 SRAM
中文描述: 512Kx36
文件頁數(shù): 2/17頁
文件大?。?/td> 335K
代理商: K7Q161862B
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
- 2 -
Rev 1.0
Mar. 2004
K7Q163662B
K7Q161862B
512Kx36-bit, 1Mx18-bit QDR
TM
SRAM
FEATURES
1.8V/2.5V +0.1V/-0.1V Power Supply.
I/O Supply Voltage 1.5V +0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Separate independent read and write data ports
with concurrent read and write operation
HSTL I/O.
Full data coherency, providing most current data .
Synchronous pipeline read with self timed early write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two Input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Single address bus.
Byte writable function.
Sepatate read/write control pin(R and W)
Simple depth expansion with no data contention.
Programmable output impedance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball aray FBGA) with body size of 13x15mm
FUNCTIONAL BLOCK DIAGRAM
R
W
BW
X
ADDRESS
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
512Kx36
1Mx18
MEMORY
ARRAY
WRITE DRIVER
K
K
36 (or 18)
4(or 2)
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7Q163662B-FC16
6.0
2.5
ns
X18
K7Q161862B-FC16
6.0
2.5
ns
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device.
72
18 (or 19)
18 (or 19)
36 (or 18)
Q(Data Out)
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.
36 (or 18)
36 (or 18)
72
(or 36)
(or 36)
相關(guān)PDF資料
PDF描述
K7Q163662B 512Kx36 & 1Mx18 QDRTM b2 SRAM
K7Q161882 512Kx36 & 1Mx18 QDR b2 SRAM
K7Q161882A 512Kx36 & 1Mx18 QDR b2 SRAM
K7Q163682A 512Kx36 & 1Mx18 QDR b2 SRAM
K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM
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