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參數(shù)資料
| 型號： | K7Q161862B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 QDRTM b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 335K |
| 代理商： | K7Q161862B |
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
- 5 -
Rev 1.0
Mar. 2004
K7Q163662B
K7Q161862B
The K7Q163662B and K7Q161862B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7Q163662B and 1,048,576 words by 18 bits for K7Q161862B.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read address is registered on rising edges of the input K clocks, and write address is
registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
0
and BW
1
( BW
2
and BW
3 )
pins.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7Q163662B and K7Q161862B are implemented with SAMSUNG's high performance 6T CMOS technology and is available
in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K instead of C and C.
When the R is disabled after a read operation, the K7Q163662B and K7Q161862B will first complete burst read operation
before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7Q163662B | 512Kx36 & 1Mx18 QDRTM b2 SRAM |
| K7Q161882 | 512Kx36 & 1Mx18 QDR b2 SRAM |
| K7Q161882A | 512Kx36 & 1Mx18 QDR b2 SRAM |
| K7Q163682A | 512Kx36 & 1Mx18 QDR b2 SRAM |
| K7R160982B | 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7Q161864B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDRTM b4 SRAM |
| K7Q161864B-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR TM b4 SRAM |
| K7Q161864B-FC16T00 | 制造商:Samsung Semiconductor 功能描述:16MSYNCQUAD DATA RATE SRAME 1MX18FBGA, T/R - Tape and Reel |
| K7Q161882 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR b2 SRAM |
| K7Q161882A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR b2 SRAM |
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