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參數(shù)資料
| 型號(hào)： | K7Q163654A-FC13 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36-bit, 1Mx18-bit QDR SRAM |
| 中文描述： | 512Kx36位，1Mx18位的國(guó)防評(píng)估報(bào)告的SRAM |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大小： | 510K |
| 代理商： | K7Q163654A-FC13 |
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512Kx36 & 1Mx18 QDR
TM
b4 SRAM
- 10 -
Rev 1.0
July. 2002
K7Q163654A
K7Q161854A
AC TIMING CHARACTERISTICS
(V
DD
=2.5V
±
0.1V, T
A
=0
°
C to +70
°
C)
Notes
: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W,BW
0
,BW
1
and (BW
2
, BW
3
, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
1
is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX
1
is a MIN parameter that is worst case at totally different test conditions
(0
°
C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70
°
C, 2.4V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER
SYMBOL
-20
-16
-13
-10
UNITS
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time(K, K, C, C)
t
KHKH
5
6
7.5
10
ns
Clock HIGH time (K, K, C, C)
t
KHKL
2.0
2.4
3.0
3.5
ns
Clock LOW time (K, K, C, C)
t
KLKH
2.0
2.4
3.0
3.5
ns
Clock to clock (K
↑ →
K
↑
, C
↑ →
C
↑
)
Clock to data clock (K
↑ →
C
↑
, K
↑→
C
↑
)
t
KHKH
2.2
2.75
2.7
3.3
3.4
4.1
4.6
5.4
ns
t
KHCH
0.0
1.7
0.0
2.0
0.0
2.5
0.0
3.0
ns
Output Times
C, C High to Output Valid
t
CHQV
2.2
2.5
3.0
3.0
ns
3
C, C High to Output hold
t
CHQX
1.0
1.2
1.2
1.2
ns
3
C High to Output High-Z
t
CHQZ
2.2
2.5
3.0
3.0
ns
3
C High to Output Low-Z
t
CHQX1
1.0
1.2
1.2
1.2
ns
3
Setup Times
Address valid to K rising edge
t
AVKH
0.6
0.7
0.8
1.0
ns
Control inputs valid to K rising edge
t
IVKH
0.6
0.7
0.8
1.0
ns
2
Data-in valid to K, K rising edge
t
DVKH
0.6
0.7
0.8
1.0
ns
Hold Times
K rising edge to address hold
t
KHAX
0.6
0.7
0.8
1.0
v
K rising edge to control inputs hold
t
KHIX
0.6
0.7
0.8
1.0
ns
K, K rising edge to data-in hold
t
KHDX
0.6
0.7
0.8
1.0
ns
V
DDQ
V
IL
V
DDQ
+0.7V
20% t
KHKH
(MIN)
V
SS
V
IH
V
SS
-0.7V
20% t
KHKH
(MIN)
Undershoot Timing
Overershoot Timing
Note:
For power-up, V
IH
≤
V
DDQ
+0.3V and V
DD
≤
2.4V and V
DDQ
≤
1.4V for t
≤
200ms
OPERATING CONDITIONS
(0
°
C
≤
T
A
≤
70
°
C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage
V
DD
2.4
2.6
V
V
DDQ
1.4
1.9
V
Reference
Voltage
V
REF
0.68
0.95
V
Ground
V
SS
0
0
V
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|---|---|
| K7Q163654A-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36-bit, 1Mx18-bit QDR SRAM |
| K7Q163654A-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36-bit, 1Mx18-bit QDR SRAM |
| K7Q163662B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDRTM b2 SRAM |
| K7Q163662B-FC16T00 | 制造商:Samsung Semiconductor 功能描述:16MSYNCQUAD DATA RATE SRAME 512KX36FBGA, T/R - Tape and Reel |
| K7Q163664B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR TM b4 SRAM |
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