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參數(shù)資料
| 型號： | K7R161882B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 428K |
| 代理商： | K7R161882B |
512Kx36 & 1Mx18 & 2Mx9 QDR
TM
II b2 SRAM
- 2 -
Rev 3.0
June. 2004
K7R163682B
K7R161882B
K7R160982B
512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDR
TM
II b2 SRAM
FEATURES
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Separate independent read and write data ports
with concurrent read and write operation
HSTL I/O
Full data coherency, providing most current data .
Synchronous pipeline read with self timed early write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write (x9, x18, x36) function.
Sepatate read/write control pin(R and W)
Simple depth expansion with no data contention.
Programmable output impenance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball array FBGA) with body size of 13x15mm
FUNCTIONAL BLOCK DIAGRAM
R
W
BW
X
ADDRESS
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
512Kx36
(1Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
36 (or 18)
4(or 2)
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7R163682B-FC25
4.0
0.45
ns
K7R163682B-FC20
5.0
0.45
ns
K7R163682B-FC16
6.0
0.50
ns
X18
K7R161882B-FC25
4.0
0.45
ns
K7R161882B-FC20
5.0
0.45
ns
K7R161882B-FC16
6.0
0.50
ns
X9
K7R160982B-FC25
4.0
0.45
ns
K7R160982B-FC20
5.0
0.45
ns
K7R160982B-FC16
6.0
0.50
ns
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
72
18
18 (or 19)
36 (or 18)
Q(Data Out)
36 (or 18)
36 (or 18)
72
(Echo Clock out)
CQ, CQ
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 19)
(or 36)
(or 36)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7R163682B | 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM |
| K7R321884M-FC16 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323684M | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323684M-FC16 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323684M-FC20 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R161884B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDRTM II b4 SRAM |
| K7R161884B-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
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