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參數(shù)資料
| 型號： | K7R161882B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 428K |
| 代理商： | K7R161882B |
512Kx36 & 1Mx18 & 2Mx9 QDR
TM
II b2 SRAM
- 6 -
Rev 3.0
June. 2004
K7R163682B
K7R161882B
K7R160982B
The K7R163682B,K7R161882B and K7R160982B are 18,874,368-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7R163682B, 1,048,576 words by 18 bits for K7R161882B and 2,097,152 words
by 9bits for K7R160982B.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address is registered on rising edges of the input K clocks, and write address is
registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
0
and BW
1
( BW
2
and BW
3)
pins for x18 ( x36 ) device and only BW pin for x9 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7R163682B,K7R161882B and K7R160982B are implemented with SAMSUNG's high performance
6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 9-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the R is disabled after a read operation, the K7R163682B,K7R161882B and K7R160982B will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
Power-Up/Power-Down Supply Voltage Sequencing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7R163682B | 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM |
| K7R321884M-FC16 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323684M | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323684M-FC16 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323684M-FC20 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R161884B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDRTM II b4 SRAM |
| K7R161884B-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
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