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參數(shù)資料
| 型號(hào)： | K7R321884M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 195K |
| 代理商： | K7R321884M |
- 4 -
Rev 2.0
Dec. 2003
1Mx36 & 2Mx18 QDR
TM
II b4 SRAM
K7R323684M
K7R321884M
PIN CONFIGURATIONS
(TOP VIEW)
K7R321884M(2Mx18)
Notes:
1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW
0
controls write to D0:D8 and BW
1
controls write to D9:D17.
PIN NAME
1
2
3
4
5
6
7
8
9
10
11
A
CQ
V
SS
/SA*
SA
W
BW
1
K
NC
R
SA
V
SS
/SA*
CQ
B
NC
Q9
D9
SA
NC
K
BW
0
SA
NC
NC
Q8
C
NC
NC
D10
V
SS
SA
NC
SA
V
SS
NC
Q7
D8
D
NC
D11
Q10
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
D7
E
NC
NC
Q11
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC
D6
Q6
F
NC
Q12
D12
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC
NC
Q5
G
NC
D13
Q13
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC
NC
D5
H
Doff
V
REF
V
DDQ
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
REF
ZQ
J
NC
NC
D14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC
Q4
D4
K
NC
NC
Q14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC
D3
Q3
L
NC
Q15
D15
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC
NC
Q2
M
NC
NC
D16
V
SS
V
SS
V
SS
V
SS
V
SS
NC
Q1
D2
N
NC
D17
Q16
V
SS
SA
SA
SA
V
SS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value
and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
SYMBOL
PIN NUMBERS
DESCRIPTION
NOTE
K, K
6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
1
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
SA
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
D0-17
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D
3F,2G,3J,3L,3M,2N
Data Inputs
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E
2F,3G,3K,2L,3N,3P
Data Outputs
W
4A
Write Control Pin,active when low
R
8A
Read Control Pin,active when low
BW
0
, BW
1
7B, 5A
Block Write Control Pin,active when low
V
REF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
2
V
DD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
V
DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V
SS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
7A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,1F
9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M
2M,9M,1N,9N,10N,1P,2P,9P
No Connect
3
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