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參數(shù)資料
| 型號(hào)： | K7R321884M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 195K |
| 代理商： | K7R321884M |
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- 7 -
Rev 2.0
Dec. 2003
1Mx36 & 2Mx18 QDR
TM
II b4 SRAM
K7R323684M
K7R321884M
STATE DIAGRAM
Notes
: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simulateneously.
4. State machine control timing sequence is controlled by K.
READ
DDR READ
D count=D count+1
POWER-UP
WRITE NOP
LOAD NEW
READ ADDRESS
D count=0
ALWAYS
WRITE
ALWAYS
READ
WRITE
READ
D count=2
INCREMENT
READ ADDRESS
READ NOP
INCREMENT
WRITE ADDRESS
DDR WRITE
D count=D count+1
LOAD NEW
WRITE ADDRESS
D count=0
ALWAYS
READ
D count=1
READ
D count=2
ALWAYS
WRITE
D count=2
WRITE
D count=1
WRITE
D count=2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7R321884M-FC20 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R321884M-FC25 | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R640982M | 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM |
| K7R641882M | Electrical, Duct/Raceway (Trunking); RoHS Compliant: Yes |
| K7R643682M | 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R321884M-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R321884M-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R321884M-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| K7R323682 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM |
| K7R323682C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
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