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參數(shù)資料
| 型號： | K7R323684M-FC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 QDRTM II b4 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 195K |
| 代理商： | K7R323684M-FC20 |
- 6 -
Rev 2.0
Dec. 2003
1Mx36 & 2Mx18 QDR
TM
II b4 SRAM
K7R323684M
K7R321884M
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with K clock.
For 4-bit burst DDR operation, it will write four 36-bit or 18-bit or 8-bit data words with each write command.
The first "late" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
The process continues until all four data are transfered and registered.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
The device disregards input data presented on the same cycle W disabled.
When the W is disabled after a read operation, the K7R323684M and K7R321884M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
The K7R323684M and K7R321884M support byte write operations.
With activating BW
0
or BW
1
( BW
2
or BW
3 )
in write cycle, only one byte of input data is presented.
In K7R321884M, BW
0
controls write operation to D0:D8, BW
1
controls write operation to D9:D17.
And in K7R323684M BW
2
controls write operation to D18:D26, BW
3
controls write operation to D27:D35.
Write Operations
Programmable Impedance Output Buffer Operation
Single Clock Mode
The K7R323684M and K7R321884M can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can’ t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently
and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
SS
through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
resistor will give an output impedance of 50
.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"
or other anomalous behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,
the SRAM needs 1024 non-read cycles.
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
Power-Up/Power-Down Supply Voltage Sequencing
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