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參數(shù)資料
| 型號： | K7R640982M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM |
| 中文描述： | 2Mx36 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 364K |
| 代理商： | K7R640982M |
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
- 2 -
Rev 0.5
Oct. 2004
Preliminary
K7R643682M
K7R641882M
K7R640982M
2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDR
TM
II b2 SRAM
FEATURES
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Separate independent read and write data ports
with concurrent read and write operation
HSTL I/O
Full data coherency, providing most current data .
Synchronous pipeline read with self timed early write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write function.
Sepatate read/write control pin(R and W)
Simple depth expansion with no data contention.
Programmable output impenance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
FUNCTIONAL BLOCK DIAGRAM
R
W
BW
X
ADDRESS
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
1Mx36
(2Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
36 (or 18, 9)
4(or 2)
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7R643682M-FC25
4.0
0.45
ns
K7R643682M-FC20
5.0
0.45
ns
K7R643682M-FC16
6.0
0.50
ns
X18
K7R641882M-FC25
4.0
0.45
ns
K7R641882M-FC20
5.0
0.45
ns
K7R641882M-FC16
6.0
0.50
ns
X9
K7R640982M-FC25
4.0
0.45
ns
K7R640982M-FC20
5.0
0.45
ns
K7R640982M-FC16
6.0
0.50
ns
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
72
20
20 (or 21, 22)
36 (or 18, 9)
Q(Data Out)
36 (or 18 ,9)
36 (or 18, 9)
(Echo Clock out)
CQ, CQ
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 21,22)
(or 36,
18)
72
(or 36,
18)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7R641882M | Electrical, Duct/Raceway (Trunking); RoHS Compliant: Yes |
| K7R643682M | 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM |
| K7R641884M | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| K7R643684M | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| K7 | KS SERIES KEY SWITCHES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R640982M-EC25000 | 制造商:Samsung SDI 功能描述: |
| K7R640982MFC25000 | 制造商:Samsung Semiconductor 功能描述: |
| K7R640982M-FC25000 | 制造商:Samsung SDI 功能描述:SRAM Chip Sync Single 1.8V 72M-Bit 8M x 9-Bit 0.45ns 165-Pin FBGA |
| K7R641882M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx36 & 4Mx18 & 8Mx9 QDR II b2 SRAM |
| K7R641882M-EC20000 | 制造商:Samsung Semiconductor 功能描述: |
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