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參數(shù)資料
| 型號(hào)： | K7R641882M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Electrical, Duct/Raceway (Trunking); RoHS Compliant: Yes |
| 中文描述： | 2Mx36 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 364K |
| 代理商： | K7R641882M |
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
- 6 -
Rev 0.5
Oct. 2004
Preliminary
K7R643682M
K7R641882M
K7R640982M
The K7R643682M,K7R641882M and K7R640982M are 75,497,472-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 2,097,152 words by 36bits for K7R643682M, 4,194,304 words by 18 bits for K7R641882M and
8,388,608 words by 9bits for K7R640982M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram on every rising edge of K and K,
and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address is registered on rising edges of the input K clocks,
and write address is registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
0
and BW
1
( BW
2
and BW
3)
pins for x18 ( x36 ) device and only BW pin for x9 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7R643682M,K7R641882M and K7R640982M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 9-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the R is disabled after a read operation, the K7R643682M,K7R641882M and K7R640982M will first complete burst read
operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7R643682M, K7R641882M, and K7R640982M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7R643682M, K7R641882M and K7R640982M support byte write operations.
With activating BW
0
or BW
1
( BW
2
or BW
3 )
in write cycle, only one byte of input data is presented.
In K7R641882M, BW
0
controls write operation to D0:D8, BW
1
controls write operation to D9:D17.
And in K7R643682M BW
2
controls write operation to D18:D26, BW
3
controls write operation to D27:D35.
And in K7R640982M BW controls write operation to D0:D8.
Write Operations
相關(guān)PDF資料 |
PDF描述 |
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| K7R641884M | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| K7R643684M | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| K7 | KS SERIES KEY SWITCHES |
| K8006 | BASE UNIT for HOME MODULAR LIGHT SYSTEM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R641882M-EC20000 | 制造商:Samsung Semiconductor 功能描述: |
| K7R641882M-EI20000 | 制造商:Samsung SDI 功能描述: |
| K7R641882M-FC16000 | 制造商:Samsung Semiconductor 功能描述:72M SYNC QDRII SRAME 4MX18FBGA - Bulk |
| K7R641882M-FC16T00 | 制造商:Samsung Semiconductor 功能描述:72M SYNC QDRII SRAME 4MX18FBGA, T/R - Tape and Reel |
| K7R641882M-FC20 | 制造商:Samsung Semiconductor 功能描述: |
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