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參數(shù)資料
| 型號： | K7R641884M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| 中文描述： | 2Mx36 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 352K |
| 代理商： | K7R641884M |
- 11 -
Rev 0.5
Oct. 2004
2Mx36 & 4Mx18 QDR
TM
II b4 SRAM
K7R643684M
K7R641884M
Preliminary
Note:
For power-up, V
IH
≤
V
DDQ
+0.3V and V
DD
≤
1.7V and V
DDQ
≤
1.4V t
≤
200ms
Undershoot Timing
Overershoot Timing
V
DDQ
/2
50
SRAM
Zo=50
0.75V
V
REF
ZQ
250
AC TEST OUTPUT LOAD
AC TEST CONDITIONS
Note
: Parameters are tested with RQ=250
Parameter
Symbol
Value
Unit
Core Power Supply Voltage
V
DD
1.7~1.9
V
Output Power Supply Voltage
V
DDQ
1.4~1.9
V
Input High/Low Level
V
IH
/V
IL
1.25/0.25
V
Input Reference Level
V
REF
0.75
V
Input Rise/Fall Time
T
R
/T
F
0.3/0.3
ns
Output Timing Reference Level
V
DDQ
/2
V
V
IL
V
DDQ
+0.5V
20% t
KHKH
(MIN)
V
SS
V
IH
V
SS
-0.5V
20% t
KHKH
(MIN)
V
DDQ
V
DDQ
+0.25V
V
SS
-0.25V
THERMAL RESISTANCE
Note
: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. T
J
=T
A
+ P
D
x
θ
JA
PRMETER
SYMBOL
TYP
Unit
°
C
/W
°
C
/W
°
C
/W
NOTES
Junction to Ambient
θ
JA
θ
JC
θ
JB
TBD
Junction to Case
TBD
Junction to Pins
TBD
PIN CAPACITANCE
Note
: 1. Parameters are tested with RQ=250
and V
DDQ
=1.5V.
2. Periodically sampled and not 100% tested.
PRMETER
SYMBOL
TESTCONDITION
TYP
MAX
Unit
NOTES
Address Control Input Capacitance
C
IN
V
IN
=0V
TBD
TBD
pF
Input and Output Capacitance
C
OUT
V
OUT
=0V
TBD
TBD
pF
Clock Capacitance
C
CLK
-
TBD
TBD
pF
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