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參數(shù)資料
| 型號： | K7R641884M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| 中文描述： | 2Mx36 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 352K |
| 代理商： | K7R641884M |
- 17 -
Rev 0.5
Oct. 2004
2Mx36 & 4Mx18 QDR
TM
II b4 SRAM
K7R643684M
K7R641884M
Preliminary
JTAG DC OPERATING CONDITIONS
Note
: 1. The input level of SRAM pin is to follow the SRAM DC specification
.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V
DD
1.7
1.8
1.9
V
Input High Level
V
IH
1.3
-
V
DD
+0.3
V
Input Low Level
V
IL
-0.3
-
0.5
V
Output High Voltage(I
OH
=-2mA)
V
OH
1.4
-
V
DD
V
Output Low Voltage(I
OL
=2mA)
V
OL
V
SS
-
0.4
V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
Note
TCK Cycle Time
t
CHCH
50
-
ns
TCK High Pulse Width
t
CHCL
20
-
ns
TCK Low Pulse Width
t
CLCH
20
-
ns
TMS Input Setup Time
t
MVCH
5
-
ns
TMS Input Hold Time
t
CHMX
5
-
ns
TDI Input Setup Time
t
DVCH
5
-
ns
TDI Input Hold Time
t
CHDX
5
-
ns
SRAM Input Setup Time
t
SVCH
5
-
ns
SRAM Input Hold Time
t
CHSX
5
-
ns
Clock Low to Output Valid
t
CLQV
0
10
ns
JTAG AC TEST CONDITIONS
Note
: 1. See SRAM AC test output load on page 11.
Parameter
Symbol
Min
Unit
Note
Input High/Low Level
V
IH
/V
IL
1.3/0.5
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
Input and Output Timing Reference Level
0.9
V
1
TCK
TMS
TDI
PI
(SRAM)
t
CHCH
t
MVCH
t
CHMX
t
CHCL
t
CLCH
t
DVCH
t
CHDX
t
CLQV
TDO
t
SVCH
t
CHSX
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