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參數資料
| 型號： | K7R641884M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| 中文描述： | 2Mx36 |
| 文件頁數： | 8/18頁 |
| 文件大?。?/td> | 352K |
| 代理商： | K7R641884M |
- 8 -
Rev 0.5
Oct. 2004
2Mx36 & 4Mx18 QDR
TM
II b4 SRAM
K7R643684M
K7R641884M
Preliminary
WRITE TRUTH TABLE
(x18)
Notes:
1. X means "Don
′
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑
).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
K
K
BW
0
BW
1
OPERATION
↑
L
L
WRITE ALL BYTEs ( K
↑
)
WRITE ALL BYTEs ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 1 ( K
↑
)
↑
L
L
↑
L
H
↑
L
H
↑
H
L
↑
H
L
WRITE BYTE 1 ( K
↑
)
WRITE NOTHING ( K
↑
)
WRITE NOTHING ( K
↑
)
↑
H
H
↑
H
H
WRITE TRUTH TABLE
(x36)
Notes:
1. X means "Don
′
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑
).
3. Assumes a WRITE cycle was initiated.
K
K
BW
0
BW
1
BW
2
BW
3
OPERATION
↑
L
L
L
L
WRITE ALL BYTEs ( K
↑
)
WRITE ALL BYTEs ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 1 ( K
↑
)
WRITE BYTE 1 ( K
↑
)
WRITE BYTE 2 and BYTE 3 ( K
↑
)
WRITE BYTE 2 and BYTE 3 ( K
↑
)
↑
L
L
L
L
↑
L
H
H
H
↑
L
H
H
H
↑
H
L
H
H
↑
H
L
H
H
↑
H
H
L
L
↑
H
H
L
L
↑
H
H
H
H
WRITE NOTHING ( K
↑
)
WRITE NOTHING ( K
↑
)
↑
H
H
H
H
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes:
1. X means "Don
′
t Care".
2. The rising edge of clock is symbolized by (
↑
).
3. Before enter into clock stop status, all pending read and write operations will be completed.
4. This signal was HIGH on previous K clock rising edge. Initating consecutive READ or WRITE operations on consecutive K clock rising edges
is not permitted. The device will ignore the second request.
5. If this signal was LOW to inititate the previous cycle, this signal becomes a don
′
t care for this operation however it is strongly recommended
that this signal is brought HIGH as shown in the truth table.
K
R
W
D
Q
OPERATION
D(A1)
D(A2)
D(A3)
D(A4)
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Stopped
X
X
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Clock Stop
↑
H
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
No Operation
↑
L
4
X
X
X
X
X
D
OUT
at C(t+1)
D
OUT
at C(t+2)
D
OUT
at C(t+2)
D
OUT
at C(t+3)
Read
↑
H
5
L
4
Din
at K(t+1)
Din
at K(t+1)
Din
at K(t+2)
Din
at K(t+2)
X
X
X
X
Write
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