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參數(shù)資料
| 型號(hào)： | K7R643684M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| 中文描述： | 2Mx36 |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大?。?/td> | 352K |
| 代理商： | K7R643684M |
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- 2 -
Rev 0.5
Oct. 2004
2Mx36 & 4Mx18 QDR
TM
II b4 SRAM
K7R643684M
K7R641884M
Preliminary
36 (or 18)
Q(Data Out)
(Echo Clock out)
CQ, CQ
72
2Mx36-bit, 4Mx18-bit QDR
TM
II b4 SRAM
FEATURES
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Separate independent read and write data ports
with concurrent read and write operation
HSTL I/O
Full data coherency, providing most current data .
Synchronous pipeline read with self timed late write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 4-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write function.
Sepatate read/write control pin(R and W)
Simple depth expansion with no data contention.
Programmable output impenance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
FUNCTIONAL BLOCK DIAGRAM
R
W
BW
X
ADDRESS
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
2Mx36
(4Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
36 (or 18)
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device.
72
19
19 (or 20)
4 (or 2)
72(or 36)
72(or 36)
144
(or 72)
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7R643684M-FC30
3.3
0.45
ns
ns
K7R643684M-FC25
4.0
0.45
K7R643684M-FC20
5.0
0.45
ns
K7R643684M-FC16
6.0
0.50
ns
X18
K7R641884M-FC30
3.3
0.45
ns
K7R641884M-FC25
4.0
0.45
ns
K7R641884M-FC20
5.0
0.45
ns
K7R641884M-FC16
6.0
0.50
ns
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 20)
(or 36)
(or 36)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| K7R643684M_07 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx36 & 4Mx18 QDR II b4 SRAM |
| K7R643684M-F20000 | 制造商:Samsung Semiconductor 功能描述: |
| K7R643684MFC25000 | 制造商:Samsung Semiconductor 功能描述: |
| K7R643684M-FC30000 | 制造商:Samsung Semiconductor 功能描述: |
| K7S1618T4C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II+ b4 SRAM |
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