
FLASH MEMORY
12
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
CAPACITANCE
(
T
A
=25
°
C, V
CC
=1.8V/3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE
:
1. The
K9F56XXX0B
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
.
Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3.
The number of initial bad blocks upon shipping does not exceed 20.
4.
Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
2013
-
2048
Blocks
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
200
500
μ
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
2
cycles
Spare Array
-
-
3
cycles
Block Erase Time
t
BERS
-
2
3
ms
AC TEST CONDITION
(K9F56XXX0B-XCB0 :TA=0 to 70
°
C, K9F56XXX0B-XIB0 :TA=-40 to 85
°
C
K9F56XXQ0B : Vcc=1.70V~1.95V , K9F56XXU0B : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F56XXQ0B
K9F56XXU0B
Input Pulse Levels
0V to VccQ
0.4V to 2.4V
Input Rise and Fall Times
5ns
5ns
Input and Output Timing Levels
VccQ/2
1.5V
K9F56XXQ0B:Output Load (VccQ:1.8V +/-10%)
K9F56XXU0B:Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
K9F56XXU0B:Output Load (VccQ:3.3V +/-10%)
-
1 TTL GATE and CL=100pF
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
GND
WP
Mode
H
L
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(3clock)
H
L
L
H
X
H
Write Mode
Command Input
L
H
L
H
X
H
Address Input(3clock)
L
L
L
H
L
H
Data Input
L
L
L
H
L
X
Data Output
L
L
L
H
H
L
X
During Read(Busy) on K9F5608U0B_Y,P or K9F5608U0B_V,F
X
X
X
X
H
L
X
During Read(Busy) on the devices except K9F5608U0B_Y,P and
K9F5608U0B_V,F
X
X
X
X
X
L
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
X
L
Write Protect
X
X
H
X
X
0V
0V/V
CC
(2)
Stand-by