- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374298 > K9F5616U0C-YIB0 (SAMSUNG SEMICONDUCTOR CO. LTD.) 512Mb/256Mb 1.8V NAND Flash Errata PDF資料下載
參數(shù)資料
| 型號： | K9F5616U0C-YIB0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mb/256Mb 1.8V NAND Flash Errata |
| 中文描述： | 512Mb/256Mb 1.8 NAND閃存勘誤表 |
| 文件頁數(shù)： | 31/39頁 |
| 文件大?。?/td> | 655K |
| 代理商： | K9F5616U0C-YIB0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
30
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-VCB0,VIB0,FCB0,FIB0
Figure 12. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com-
mand(60h). Only address A
14
to A
24
is valid while A
9
to A
13
is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
60h
Block Add. : A
9
~ A
24
R/B
Address Input(2Cycle)
I/O
0
Pass
D0h
70h
Fail
t
BERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
Status
Definition
I/O 0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
Reserved for Future
Use
"0"
I/O 2
"0"
I/O 3
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
"0" : Busy "1" : Ready
I/O 7
Write Protect
"0" : Protected "1" : Not Protected
I/O 8~15
Not use
Don’t care
I/Ox
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K9F1208Q0A | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; Number of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| K9F5608U0M-YCB0 | 32M x 8 Bit NAND Flash Memory |
| K9F5608U0M-YIB0 | 32M x 8 Bit NAND Flash Memory |
| K9F5608U0M- | 32M x 8 Bit NAND Flash Memory |
| K9F5616Q0B-DCB0 | SCSI-5 MALE SCSI-3 MALE CABLE 10 FT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K9F56XXQ0C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 8 Bit 16M x 16 Bit NAND Flash Memory |
| K9F6408Q0C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit Bit NAND Flash Memory |
| K9F6408Q0C-B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit Bit NAND Flash Memory |
| K9F6408Q0C-H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit Bit NAND Flash Memory |
| K9F6408U0A-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。