參數(shù)資料
型號(hào): KFG5616Q1M-DEB
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: OneNAND256
中文描述: OneNAND256
文件頁數(shù): 79/93頁
文件大?。?/td> 1223K
代理商: KFG5616Q1M-DEB
OneNAND256
FLASH MEMORY
79
10.3 Asynchronous Read
NOTE:
1. If OE is disabled at the same time or before CE is disabled, the output will go to high-z by t
OEZ
(max. 17ns).
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by t
CEZ
(max. 20ns).
If CE and OE are disabled at the same time, the output will go to high-z by t
OEZ
(max. 17ns).
These parameters are not 100% tested.
Parameter
Symbol
KFG5616X1M
Unit
Min
Max
Access Time from CE Low
t
CE
-
76
ns
Asynchronous Access Time from AVD Low
t
AA
-
76
ns
Asynchronous Access Time from address valid
t
ACC
-
76
ns
Read Cycle Time
t
RC
76
-
ns
AVD Low Time
t
AVDP
12
-
ns
Address Setup to rising edge of AVD
t
AAVDS
7
-
ns
Address Hold from rising edge of AVD
t
AAVDH
7
-
ns
Output Enable to Output Valid
t
OE
-
20
ns
CE Setup to AVD falling edge
t
CA
0
-
ns
CE Disable to Output & RDY High Z
1)
t
CEZ
-
20
ns
OE Disable to Output & RDY High Z
1)
t
OEZ
-
17
ns
SWITCHING WAVEFORMS
Figure 30. Asynchronous Read Mode(AVD toggling)
NOTE:
VA=Valid Read Address, RD=Read Data.
t
OE
VA
Valid RD
t
CE
t
OEZ
CE
OE
WE
A0-A15
CLK
V
IL
AVD
Hi-Z
Hi-Z
RDY
t
AVDP
t
AAVDH
DQ0-DQ15
t
CEZ
Case 1 : Valid Address and AVD Transition occur before CE is driven to Low
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