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參數(shù)資料
| 型號(hào)： | KFM1216Q2M-DED |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 閃存 |
| 文件頁(yè)數(shù)： | 38/88頁(yè) |
| 文件大?。?/td> | 1150K |
| 代理商： | KFM1216Q2M-DED |
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MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
38
7.21 Interrupt Status Register (R/W): F241h,
default=8080h(after Cold reset),8010h(after Warm/Hot reset)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Reserved(0000000)
RI
WI
EI
RSTI
Reserved(0000)
7.22 Start Block Address (R/W): F24Ch, default=0000h
SBA
(Start Block Address): Start NAND Flash block address to unlock in Write Protection mode, which preceeds ’Unlock block command’.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000)
SBA
7.23 End Block Address (R/W): F24Dh, default=0000h
EBA
(End Block Address): End NAND Flash block address to unlock in Write Protection mode, which preceeds ’Unlock block command’. EBA should be
equal to or larger than SBA.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000)
EBA
Device
Number of Block
SBA/EBA
512Mb
512
[8:0]
Bit
Address
Bit Name
Default State
Cold
1
Valid
States
Function
Warm/Hot
1
15
INT(interrupt): the master interrupt bit
- Set to ’1’ of itself when one or more of RI, WI, EI and
RSTI is set to ’1’, or Unlock(0023h), Lock(002Ah), Lock-
tight(002Ch) or OTP access(0075h - 0065h) operation,
or "Load Data into Buffer" is completed.
- Cleared to ’0’ when by writing ’0’ to this bit or by
reset(Cold/Warm/Hot reset).
’0’ in this bit means that INT pin is low status.
(This INT bit is directly wired to the INT pin on the chip.
INT pin goes low upon writing ’0’ to this bit when
INTpol is high and goes high upon writing ’0’ to this
bit when INTpol is low. )
RI(Read Interrupt):
- Set to ’1’ of itself at the completion of Load Operation
(0000h, 0013h, or boot is done.)
- Cleared to ’0’ when by writing ’0’ to this bit or by reset
(Cold/Warm/Hot reset).
WI(Write Interrupt):
- Set to ’1’ of itself at the completion of Program Operation
(0080h, 001Ah, or 001Bh)
- Cleared to ’0’ when by writing ’0’ to this bit or by reset
(Cold/Warm/Hot reset).
EI(Erase Interrupt):
- Set to ’1’ of itself at the completion of Erase Operation
(0094h)
- Cleared to ’0’ when by writing ’0’ to this bit or by reset
(Cold/Warm/Hot reset).
RSTI(Reset Interrupt):
- Set to ’1’ of itself at the completion of Reset Operation
(00F0h, 00F3h, or warm reset is released.)
- Cleared to ’0’ when by writing ’0’ to this bit.
0
Interrupt Off
Interrupt Pending
0->1
7
1
0
0
Interrupt Off
Interrupt Pending
0->1
6
0
0
0
Interrupt Off
Interrupt Pending
0->1
5
0
0
0
Interrupt Off
Interrupt Pending
0->1
4
0
1
0
Interrupt Off
Interrupt Pending
0->1
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