參數(shù)資料
型號： KFM1216Q2M
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： FLASH MEMORY
中文描述： 閃存
文件頁數(shù)： 35/88頁
文件大?。?/td> 1150K
代理商： KFM1216Q2M
MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
35
7.18 System Configuration 1 Register (R, R/W): F221h, default=40C0h
RM
(Read Mode): this field specifies the selection between asynchronous read mode and synchronous read mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
RM
BRL
BL
ECC
RDY
pol
INT
pol
IOB
E
Reserved(0000)
BW
PS
RM
Read Mode
0
Asynchronous read(default)
1
Synchronous read
BRL
Latency Cycles
000
8(N/A)
001
9(N/A)
010
10(N/A)
011
3(N/A)
100
4(default, min.)
101
5
110
6
111
7
BRL
(Burst Read Latency): this field specifies the initial access latency in the burst read transfer.
BL
Burst Length(Main)
Burst Length(Spare)
000
Continuous(default)
001
4 words
010
8 words
011
16 words
100
32 words
N/A
101~111
Reserved
BL
(Burst Length): this field specifies the size of burst length during Sync. burst read. Wrap around and linear burst.
ECC
: Error Correction Operation,
0=with correction(default), 1=without correction(by-passed)
RDYpol
: RDY signal polarity
0=low for ready, 1=high for ready((default)
INTpol
: INT signal polarity
0=low for Interrupt pending , 1=high for Interrupt pending (default)
IOBE
: I/O buffer enable for INT and RDY signals, INT and RDY outputs are HighZ at start up, bit 7 and 6 become valid after IOBE is set to1.
IOBE can be reset only by Cold reset or by writing 0 to bit 5 of System Configuration 1 register.
0=disable(default), 1=enable
BWPS
: boot buffer write protect status,
0=locked(default)
INTpol
INT bit of Interrupt Status Register
INT Pin output
0
0
1
1
0
0
相關(guān)PDF資料
PDF描述
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