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參數(shù)資料
| 型號： | KFM1216Q2M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 閃存 |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 1150K |
| 代理商： | KFM1216Q2M |
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MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
53
8.6.5 Programmable Burst Read Latency
The programmable burst read latency feature indicates to the device the number of additional clock cycles that must elapse after
AVD is driven active before data will be available. Upon power up, the number of total initial access cycles defaults to four clocks. The
number of total initial access cycles is programmable from four to seven cycles.
8.6.4 4-, 8-,16-, 32- Word Linear Burst Read
As well as the Continuous Linear Burst Mode, there are four(4 & 8 & 16 & 32 word) (Note1) linear wrap-around mode, in which a fixed
number of words are read from consecutive addresses. When the last word in the burst mode is reached, assert /CE and /OE high to
terminate the operation. In these modes, the start address for burst read can be any address of address map.
(Note 1) 32 word linear burst read isn’t available on spare area BufferRAM
Figure 13. Example of 4clock Busrt Read Latency
Table 7. Burst Address Sequences
Start
Addr.
Burst Address Sequence(Decimal)
Continuous Burst
4-word Burst
8-word Burst
16-word Burst
32-word Burst
Wrap
around
0
0-1-2-3-4-5-6...
0-1-2-3-0...
0-1-2-3-4-5-6-7-0...
0-1-2-3-4-....-13-14-15-0...
0-1-2-3-4-....-29-30-31-0...
1
1-2-3-4-5-6-7...
1-2-3-0-1...
1-2-3-4-5-6-7-0-1...
1-2-3-4-5-....-14-15-0-1...
1-2-3-4-5-....-30-31-0-1...
2
2-3-4-5-6-7-8...
2-3-0-1-2...
2-3-4-5-6-7-0-1-2...
2-3-4-5-6-....-15-0-1-2...
2-3-4-5-6-....-31-0-1-2...
.
.
.
.
.
.
.
.
.
.
.
.
8.6.6 Handshaking
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word
of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable
burst read latency configuration.(See "System Configuration1 Register" for details.) The rising edge of RDY which is derived from 1
clock ahead of data fetch clock indicates the initial word of valid burst data.
8.6.7 Output Disable Mode
When the CE or OE input is at V
IH
, output from the device is disabled. The outputs are placed in the high impedance state.
t
IAA
Hi-Z
CE
CLK
AVD
OE
RDY
≈
≈
t
RDYS
t
RDYA
A/DQ0:
A/DQ15
D6
D7
D0
D1
D2
D3
D7
D0
Hi-Z
≈
≈
≈
Valid
Address
0
1
2
3
4
t
BA
Rising edge of the clock cycle following last read latency
triggers next burst data
-1
5
6
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