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參數(shù)資料
| 型號： | KFM1216Q2M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 閃存 |
| 文件頁數(shù)： | 65/88頁 |
| 文件大小： | 1150K |
| 代理商： | KFM1216Q2M |
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MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
65
8.14 ECC Operation
While the device transfers data from BufferRAM to NAND Flash Array Page Buffer for Program Operation, the device hiddenly gener-
ates ECC(24bits for main area data and 10bits for 2nd and 3rd word data of each sector spare area) and while Load operation, hid-
denly generates ECC and detects error number and position and corrects 1bit error. ECC is updated by the device automatically.
After Load Operation, host can know whether there is error or not by reading ’ECC Status Register’(refer to ECC Status Register
Table). In addition, OneNAND supports 2bit EDC even though it is little probable that 2bit error occurs. Hence, it is not recommeded
that Host reads ’ECC Status Register’ for checking ECC error because the built-in Error Correction Logic of OneNAND finds out and
corrects ECC error.
When the device loads NAND Flash Array main and sprea area data with ECC operation, the device does not place the newly gener-
ated ECC for main and spare area into the buffer but places ECC which was generated and written in program operation into the
buffer.
Ecc operation is done during the boot loading operation.
8.14.1 ECC Bypass Operation
ECC bypass operation is set by 9th bit of System Configuration 1 register. In ECC Bypass operation, the device neither generates
ECC result which indicates error position nor updates ECC code to NAND Flash arrary spare area in program operation(refer to ECC
Result Register Tables). During Load operation, the on-chip ECC engine does not generate a new ECC internally and the values of
ECC Status and Result Registers are invalid. Hence, in ECC Bypass operation, the error cannot be detected and corrected by Mux-
OneNAND itself. ECC Bypass operation is not recommended to host.
Table 8. ECC Code & Result Status by ECC operation mode
NOTE:
1. Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation.
Operation
Program operation
Load operation
ECC Code Update to NAND
Flash Array Spare Area
ECC Code at BufferRAM Spare
Area
ECC Status & Result Update
to Registers
1bit Error
ECC operation
Update
Pre-written ECC code
(1)
loaded
Update
Correct
ECC bypass
Not update
Pre-written code loaded
Invalid
Not correct
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