參數(shù)資料
型號： KH561AM
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 運(yùn)動控制電子
英文描述： Wideband, Low Distortion Driver Amplifier
中文描述： OP-AMP, 5000 uV OFFSET-MAX, CDIP24
封裝： CERAMIC, DIP-24
文件頁數(shù)： 6/13頁
文件大?。?/td> 182K
代理商： KH561AM
DATA SHEET
KH561
6
REV. 1A February 2001
SUMMARY DESIGN EQUATIONS AND DEFINITIONS
KH561 Description of Operation
Looking at the circuit of Figure 1 (the topology and
resistor values used in setting the data sheet specifica-
tions), the KH561 appears to bear a strong external
resemblance to a classical op amp.
simplified block diagram of Figure 2, however, it differs in
several key areas. Principally, the error signal is a
current into the inverting input (current feedback) and the
forward gain from this current to the output is relatively
low, but very well controlled, current gain. The KH561
has been intentionally designed to have a low internal
gain and a current mode output in order that an equivalent
output impedance can be achieved without the series
matching resistor more commonly required of low output
impedance op amps. Many of the benefits of a high loop
gain have, however, been retained through a very careful
control of the KH561
’
s internal characteristics.
As shown in the
The feedback and gain setting resistors determine both
the output impedance and the gain. R
f
predominately
sets the output impedance (R
o
), while R
g
predominately
determines the no load gain (A
v
). solving for the required
R
f
and R
g
, given a desired R
o
and A
v
, yields the design
equations shown below. Conversely, given an R
f
and R
g
,
the performance equations show that both R
f
and R
g
play
a part in setting R
o
and A
v
.
adjustment would be possible if the inverting input imped-
ance (R
i
) were 0 but, with R
i
= 14
as shown in the
specification listing, independent gain and output imped-
ance setting is not directly possible.
Independent R
o
and A
v
Figure 1:Test Circuit
Design Equations
Performance Equations
Simplified Circuit Description
Looking at the KH561
’
s simplified schematic in Figure 2,
the amplifier
’
s operation may be described. Going from
the non-inverting input at pin 8 to the inverting input at pin
18, transistors Q1
–
Q4 act as an open loop unity gain
buffer forcing the inverting node voltage to follow the non-
inverting voltage input.
Transistors Q3 and Q4 also act as a low impedance (14
looking into pin 18) path for the feedback error current.
This current, (i
err
), flows through those transistors into a
very well defined current mirror having a gain of 10 from
this error current to the output.The current mirror outputs
act as the amplifier output.
The input stage bias currents are supply voltage inde-
pendent. Since these set the bias level for the whole
R
f
–
Feedback resistor
from output to inverting
input
R
g
–
Gain setting
resistor from inverting
input to ground
C
x
–
External
compensation capacitor
from output to
pin 19 (in pF)
Where:
R
o
–
Desired equivalent output impedance
A
v
–
Non-inverting input to output voltage
gain with no load
G
–
Internal current gain from inverting input
to output = 10 ±1%
R
i
–
Internal inverting input impedance = 14
±%5
R
s
–
Non-inverting input termination resistor
R
L
–
Load resistor
A
L
–
Voltage gain from non-inverting input to
load resistor
R
G 1 R
A R
R
R
R
A
1
C
1
R
300 1
2
R
0.08
f
o
i
g
f
o
v
x
o
g
=
(
=
=
6.8
μ
F
.1
μ
F
-V
CC
(-15)
410
R
g
40
5,10,15,
20
R
f
21
KH561
-
+
18
R
s
50
8
V
i
(P
i
)
R
L
50
V
o
(P
o
)
R
o
419
+V
CC
(+15)
.1
μ
F
6.8
μ
F
+
+
C
x
23
10.5pF
Resistor Values
shown result in:
Ro = 50
Av = +10
(no-load gain)
A
= +5 [14dB]
(gain to 50
load)
R
G 1 R
A R
R
R
R
A
1
f
o
i
g
f
o
v
=
(
=
R
R
R 1
R
R
G 1
R
R
A
1
R
R
G
R
R
G 1
R
R
o
f
f
g
i
g
v
f
g
i
f
i
g
=
+
+
= +
Where:
G
≡
forward current gain
(=10)
R
i
≡
inverting node input
resistance (=14
)
R
o
≡
desired output
impedance
A
v
≡
desired non-
inverting voltage
gain with no load
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