參數(shù)資料
型號(hào)： KM23C32005BG
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 32M-Bit (4Mx8 /2Mx16) CMOS Mask ROM(32M位 (4Mx8 /2Mx16) CMOS掩膜ROM)
中文描述： 32兆位（4Mx8 / 2Mx16）的CMOS掩模ROM（32兆位（4Mx8 / 2Mx16）的CMOS掩膜光盤）
文件頁(yè)數(shù)： 1/5頁(yè)
文件大?。?/td> 67K
代理商： KM23C32005BG
KM23C32005BG
CMOS MASK ROM
Pin Name
Pin Function
A
0
- A
2
Page Address Inputs
A
3
- A
20
Address Inputs
Q
0
- Q
14
Data Outputs
Q
15
/A
-1
Output 15(Word mode)/
LSB Address(Byte mode)
BHE
Word/Byte selection
CE
Chip Enable
OE
Output Enable
V
CC
Power ( +5V)
V
SS
Ground
N.C
No Connection
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
The KM23C32005BG is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 4,194,304x8 bit(byte mode) or as
2,097,152x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows four to eight words of data to read fast in the same page,
CE and A
3
~ A
20
should not be changed.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The KM23C32005BG is packaged in a 44-SOP.
GENERAL DESCRIPTION
FEATURES
Switchable organization
4,194,304x8(byte mode)
2,097,152x16(word mode)
Fast access time
Random Access : 100ns(Max.)
Page Access : 30ns(Max.)
Supply voltage : single +5V
Current consumption
Operating : 150mA(Max.)
Standby : 50
μ
A(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. KM23C32005BG : 44-SOP-600
PIN CONFIGURATION
N.C
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
V
SS
OE
Q
0
Q
8
Q
1
Q
9
Q
4
Q
12
Q
5
Q
13
Q
6
V
SS
Q
14
Q
7
Q
15
/A
-1
SOP
KM23C32005BG
FUNCTIONAL BLOCK DIAGRAM
1
2
44
43
42
3
4
41
5
6
40
39
38
7
8
37
36
9
10
35
34
11
12
33
32
13
14
31
30
15
16
29
28
17
18
27
26
19
20
25
24
21
22
23
Q
2
Q
10
Q
3
Q
11
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BHE
V
CC
A
20
X
A
0~
A
2
A
-1
AND
DECODER
BUFFERS
A
3
Y
AND
DECODER
BUFFERS
MEMORY CELL
MATRIX
(2,097,152x16/
4,194,304x8)
SENSE AMP.
CONTROL
LOGIC
DATA OUT
BUFFERS
CE
OE
BHE
.
.
.
.
.
.
.
.
Q
0
/Q
8
Q
7
/Q
15
. . .
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