參數(shù)資料
型號(hào): KM23SV32205T
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x32 Synchronous MASK ROM(1M×32位同步掩膜ROM)
中文描述: 100萬X32號(hào),同步掩膜ROM(100萬× 32位同步掩膜光盤)
文件頁數(shù): 1/25頁
文件大?。?/td> 493K
代理商: KM23SV32205T
KM23SV32205T
Synch. MROM
Preliminary
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Switchable organization
2,097,152 x 16(word mode) /
1,048,576 x 32(double word mode)
All inputs are sampled at the rising edge of the system clock
Read Performance from memory point of view
4-1-1-1 @33MHz (RAS Latency=1, CAS Latency=3)
5-1-1-1 @50MHz (RAS Latency=1, CAS Latency=4)
7-1-1-1 @66MHz (RAS Latency=2, CAS Latency=5)
t
SAC
: 10ns(Targetting 9ns)
MRS cycle with address key programs
-. RAS Latency(1 & 2)
-. CAS Latency(2 ~ 6)
-. Burst Length : 4, 8
-. Burst Type : Sequential & Interleaved
DQM for data-out masking
Package :86-TSOP2 - 400
GENERAL DESCRIPTION
The KM23SV32205T is a synchronous high bandwidth mask
programmable ROM fabricated with SAMSUNG
s high perfor-
mance CMOS process technology and is organized either as
2,097,152 x16bit(word mode) or as 1,048,576 x32bit(double
word mode) depending on polarity of WORD pin.(see pin func-
tion description). Synchronous design allows precise cycle con-
trol, with the use of system clock, I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
FEATURES
1M x32 Synchronous MASKROM
ORDERING INFORMATION
Part NO.
MAX Freq.
Interface
Package
KM23SV32205T-15
66MHz
LVTTL
86TSOP2
KM23SV32205T-20
50MHz
KM23SV32205T-30
33MHz
FUNCTIONAL BLOCK DIAGRAM
*
Samsung Electronics reserves the right to
change products or specification without notice.
Timing Register
1M x 32
S
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
C
L
LCKE
LRAS
LMR
CLK
CKE
MR
RAS
CAS
CS
CLK
ADD
LCAS
Output Buffer
. . .
Q0
Q16
Q15
Q31
Cell Array
DQM
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