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參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 16/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 17
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
ROW-to-ROW Examples
Figure Figure shows examples of some of the the ROW-to-
ROW packet spacings from Table Table. A complete
sequence of activate and precharge commands is directed to a
bank. The RR8 and RR12 rules apply to this sequence. In
addition to satisfying the t
RAS
and t
RP
timing parameters, the
separation between ACT commands to the same bank must
also satisfy the t
RC
timing parameter (RR4).
When a bank is activated, it is necessary for adjacent banks
to remain precharged. As a result, the adjacent banks will
also satisfy parallel timing constraints; in the example, the
RR11 and RR3 rules are analogous to the RR12 and RR4
rules.
Figure Figure shows examples of the ACT-to-ACT (RR1,
RR2) and ACT-to-PRER (RR5, RR6) command spacings
from Table Table. In general, the commands in ROW packets
may be spaced an interval t
PACKET
apart unless they are
directed to the same or adjacent banks or unless they are a
similar command type (both PRER or both ACT) directed to
the same device.
Figure 10 : Row Packet Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
PRER a1
t
RAS
t
RC
a0 = {Da,Ba,Ra}
a1 = {Da,Ba+1}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
Same Device
Same Device
Same Device
Adjacent Bank
Adjacent Bank
Same Bank
RR7
RR3
RR4
t
RP
Same Device
Same Device
Adjacent Bank
Same Bank
RR11
RR12
ACT b0
Figure 11 : Row Packet Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
PRER b0
t
PACKET
ACT c0
t
RR
a0 = {Da,Ba,Ra}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
Different Device
Same Device
Different Device
Same Device
Any Bank
Non-adjacent Bank
Any Bank
Non-adjacent Bank
RR1
RR2
RR5
RR6
ACT a0
ACT a0
ACT b0
PRER c0
ACT a0
t
PACKET
t
PACKET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416RD4D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK80 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(DB)-RCG60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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