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參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 17/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 18
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
Figure Figure shows examples of the PRER-to-PRER
(RR13, RR14) and PRER-to-ACT (RR9, RR10) command
spacings from Table 10. The RR15 and RR16 cases (PRER-
to-PRER to same or adjacent banks) are not shown, but are
similar to RR14. In general, the commands in ROW packets
may be spaced an interval t
PACKET
apart unless they are
directed to the same or adjacent banks or unless they are a
similar command type (both PRER or both ACT) directed to
the same device.
Row and Column Cycle Description
Activate:
A row cycle begins with the activate (ACT) opera-
tion. The activation process is destructive; the act of sensing
the value of a bit in a bank’s storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.
Restore:
Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.
Read/Write:
While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.
Precharge:
When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.
Intervals:
The activate operation requires the interval
t
RCD,MIN
to complete. The hidden restore operation requires
the interval t
RAS,MIN
- t
RCD,MIN
to complete. Column read
and write operations are also performed during the t
RAS,MIN
- t
RCD,MIN
interval (if more than about four column opera-
tions are performed, this interval must be increased). The
precharge operation requires the interval t
RP,MIN
to
complete.
Adjacent Banks:
An RDRAM with a “d” designation
(256Kx16dx16/18) indicates it contains “doubled banks”.
This means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0 and sense amp
15 are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that
bank and are not available for use by the two adjacent banks.
These two adjacent banks must remain precharged while the
selected bank goes through its activate, restore, read/write,
and precharge operations.
For example (referring to the block diagram of Figure 2), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 512 bytes
loaded into each sense amp from the 1Kbyte row - 256 bytes
to the DQA side and 256 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.
Figure 12 : Row Packet Examples
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
PRER a0
ACT b0
t
PACKET
PRER c0
a0 = {Da,Ba,Ra}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
c0 = {Da,Ba,Rc}
Different Device
Same Device
Same Device
Any Bank
Non-adjacent Bank
Adjacent Bank
RR13
RR14
RR15
PRER a0
PRER a0
PRER b0
ACT c0
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
Different Device
Same Device
Any Bank
Non-adjacent Bank
RR9
RR10
PRER a0
c0 = {Da,Ba+1Rc}
Same Device
Same Bank
RR16
t
PP
t
PACKET
t
PACKET
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相關(guān)代理商/技術(shù)參數(shù) |
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| KM416RD4D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK80 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(DB)-RCG60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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